七段译码器(用VHDL语言编写七段显示译码器，输入
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共阴极数码管libraryieee;useieee.std_logic_1164.all;entityseven_segisport(D:instd_logic_vector(3donto0);--4bitslatchinputX:outstd_logic_vector(6donto0);--tosevensegment);endseven_seg;architecturearch_seven_segofseven_segisbeginprocess(D)begincaseDishen"0000"=>X<="1111110";--0numbertoshohen"0001"=>X<="0110000";--1hen"0010"=>X<="1101101";--2hen"0011"=>X<="1111001";--3hen"0100"=>X<="0110011";--4hen"0101"=>X<="1011011";--5hen"0110"=>X<="1011111";--6hen"0111"=>X<="1110000";--7hen"1000"=>X<="1111111";--8hen"1001"=>X<="1111011";--9henOTHERS=>X<=(OTHERS=>'0');endcase;endprocess;endarch_seven_seg;